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mitsubishi electric m5m5v416btp,rt revision-p0 4 , ' 98.12.16 4194304-bit (262144-word by 16-bit) cmos static ram mitsubishi lsis preliminary notice: this is not a final specification. some parametric limits are subject to change description features the m5m5v416b is a family of low voltage 4-mbit static rams organized as 262,144-words by 16-bit, fabricated by mitsubishi's high-performance 0.25m cmos technology. the m5m5v416b is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. m5m5v416btp,rt are packaged in a 44-pin 400mil thin small outline package. m5m5v416btp (normal lead bend type package) , m5m5v416brt (reverse lead bend type package) , both types are very easy to design a printed circuit board. from the point of operating temperature, the family is divided into three versions; "standard", "w-version", and "i-version". those are summarized in the part name table below. single +2.7~+3.6v power supply small stand-by current: 0.3a(3v,typ.) no clocks, no refresh data retention supply voltage=2.0v to 3.6v all inputs and outputs are ttl compatible. easy memory expansion by s1, s2, bc1 and bc2 common data i/o three-state outputs: or-tie capability oe prevents data contention in the i/o bus process technology: 0.25m cmos package: 44 pin 400mil tsop (ii) pin configuration * "typical" parameter is sampled, not 100% tested. outline: 44p3w-h/j nc: no connection a0 ~ a17 dq1 ~ dq16 s1 w oe bc1 address input data input / output chip select input 1 write control input output enable input lower byte (dq1 ~ 8) pin function vcc gnd power supply ground supply bc2 upper byte (dq9 ~ 16) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 s1 dq1 vcc gnd we a2 a1 a0 dq2 dq3 dq4 dq5 dq6 dq7 dq8 a15 a14 a13 a12 a16 bc1 oe bc2 a5 s2 a8 a9 a10 a11 dq9 dq10 dq11 dq12 vcc gnd dq13 dq14 dq15 dq16 a6 a7 a17 bc1 oe a4 a3 bc2 s1 a5 dq1 s2 vcc gnd we a8 a9 a10 a11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a2 a1 a0 dq2 dq3 dq4 dq5 dq6 dq7 dq8 a15 a14 a13 a12 a16 dq9 dq10 dq11 dq12 vcc gnd dq13 dq14 dq15 dq16 a6 a7 a17 s2 chip select input 2 85ns 100ns 70ns 100ns 100ns 100ns 70ns 2.7 ~ 3.6v 2.7 ~ 3.6v 2.7 ~ 3.6v 2.7 ~ 3.6v 2.7 ~ 3.6v 2.7 ~ 3.6v --- --- --- 0.3a 0.3a 0.3a --- 1a 1a 3a 1a 3a --- --- --- 1a 1a 1a --- --- 20a 10a 20a 10a 40a 20a 20a 10a 40a 20a --- --- --- --- --- 3a 40ma (10mhz) 5ma (1mhz) 85ns 100ns 85ns 70ns 85ns 85ns 100ns 85ns 70ns 70ns 70ns m5m5v416btp , rt -85l m5m5v416btp , rt -70l m5m5v416btp , rt -10l m5m5v416btp , rt -70h m5m5v416btp , rt -85h m5m5v416btp , rt -10h m5m5v416btp , rt -85lw m5m5v416btp , rt -70lw m5m5v416btp , rt -10lw m5m5v416btp , rt -85hw m5m5v416btp , rt -70hw m5m5v416btp , rt -10hw m5m5v416btp , rt -85li m5m5v416btp , rt -70li m5m5v416btp , rt -10li m5m5v416btp , rt -85hi m5m5v416btp , rt -70hi m5m5v416btp , rt -10hi version, operating temperature standard 0 ~ +70c w- version -20 ~ +85c i- version -40 ~ +85c part name power supply access time max. stand-by current icc (pd) , vcc=3.0v typical * ratings (max.) active current (3.0v, typ.) icc1 70c 85c 25c 25c 40c 40c 1 44p3w-h 44p3w-j
mitsubishi electric m5m5v416btp,rt revision-p0 4 , ' 98.12.16 4194304-bit (262144-word by 16-bit) cmos static ram mitsubishi lsis preliminary notice: this is not a final specification. some parametric limits are subject to change 2 function the m5m5v416btp,rt are organized as 262,144-words by 16-bit. these devices operate on a single +2.7~3.6v power supply, and are directly ttl compatible to both input and output. its fully static circuit needs no clocks and no refresh, and makes it useful. the operation mode are determined by a combination of the device control inputs bc1 , bc2 , s1, s2 , w and oe. each mode is summarized in the function table. a write operation is executed whenever the low level w overlaps with the low level bc1 and/or bc2 and the low level s1 and the high level s2. the address(a0~a17) must be set up before the write cycle and must be stable during the entire cycle. a read operation is executed by setting w at a high level and oe at a low level while bc1 and/or bc2 and s1 and s2 are in an active state(s1=l,s2=h). when setting bc1 at the high level and other pins are in an active stage , upper-byte are in a selectable mode in which both reading and writing are enabled, and lower-byte are in a non-selectable mode. and when setting bc2 at a high level and other pins are in an active stage, lower- byte are in a selectable mode and upper-byte are in a non-selectable mode. when setting bc1 and bc2 at a high level or s1 at a high level or s2 at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high-impedance state, allowing or-tie with other chips and memory expansion by bc1, bc2 and s1, s2. the power supply current is reduced as low as 0.3a(25 c , typical), and the memory data can be held at +2v power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. block diagram memory array 262144 words x 16 bits clock generator a 0 a 1 a 16 a 17 s2 bc1 bc2 w oe dq 8 dq 1 dq 16 dq 9 - vcc gnd s1 function table mode s2 w h x x high-z bc1 bc2 oe dq1~8 x x non selection dq9~16 icc high-z standby high-z high-z h x l l h din high-z active h h l h read high-z dout active l h h l active h h l active h l high-z high-z active h l h h high-z h l dout h l l read dout active h l din l l x write din active h high-z h h high-z high-z non selection x h h x x standby write h h l l write din active x h l h read high-z active l dout h high-z s1 h l l l l l l l x l l l x x high-z x x non selection high-z standby l l x x high-z x x non selection high-z standby h
mitsubishi electric m5m5v416btp,rt revision-p0 4 , ' 98.12.16 4194304-bit (262144-word by 16-bit) cmos static ram mitsubishi lsis preliminary notice: this is not a final specification. some parametric limits are subject to change 3 absolute maximum ratings pf 10 v i =gnd, v i =25mvrms, f=1mhz v o = gnd,v o =25mvrms, f=1mhz c i c o symbol parameter limits conditions units a ma a ma v icc 1 icc 2 icc 4 v ih v il i o icc 3 v oh1 i oh = -0.5ma v oh2 i oh = -0.05ma v ol i ol =2ma i i v i =0 ~ vcc bc1 and bc2=v ih or s1=v ih or s2=v ih or oe=v ih , v i/o =0 ~ vcc vcc+0.3v 0.6 2.2 -0.3 * 2.4 0.5 0.4 1 5 0 4 0 12 vcc-0.5v 1 10 -hw, -hi max typ min dc electrical characteristics +70c +40 ~ +70c +25 ~ +40c 0.3 f= 10mhz f= 1mhz - - - - - - - - - - supply voltage input voltage output voltage power dissipation operating temperature storage temperature v mw conditions ta=25c 700 - 20 ~ +85 - 65 ~ +150 ratings v cc v i v o p d t a t stg -0.5 * ~ +4.6 -0.5 * ~ vcc + 0.5 0 ~ vcc symbol parameter units - 40 ~ +85 0 ~ +70 standard w-version i-version with respect to gnd f= 10mhz f= 1mhz 5 5 0 4 0 10 5 +70 ~ +85c +70 ~ +85c -l, -lw, -li - 20 ~ +25c - 40 ~ +25c -h, -hw, -hi 0 ~ +25c -h -hw -hi - -lw, -li - - 0.3 0.3 1 1 .2 3.6 - - - - 24 24 48 - (-l, -h) (-lw, -hw) (-li, -hi) with respect to gnd with respect to gnd ( vcc=2.7 ~ 3.6v, unless otherwise noted) high-level input voltage low-level input voltage high-level output voltage 1 high-level output voltage 2 low-level output voltage input leakage current output leakage current active supply current ( ac,mos level ) ( ac,ttl level ) active supply current stand by supply current ( ac,mos level ) ( ac,ttl level ) stand by supply current other inputs= 0 ~ vcc * -3.0v in case of ac (pulse width 30ns) note 1: direction for current flowing into ic is indicated as positive (no mark) note 2: typical value is for vcc=3.0v and ta=25 c capacitance (vcc=2.7 ~ 3.6v, unless otherwise noted) symbol parameter conditions limits max typ min units input capacitance output capacitance * -3.0v in case of ac (pulse width 30ns) bc1 and bc2 0.2v, s1 0.2v, s2 vcc-0.2v other inputs 0.2v or vcc-0.2v output - open (duty 100%) < = < = > = bc1 and bc2=v il , s=v il ,s2=v ih < = other pins =v ih or v il output - open (duty 100%) other inputs=0~vcc s1 vcc - 0.2v, other inputs = 0 ~ vcc > = > = s1 0.2v, s2 vcc - 0.2v < = < 1 > < 3 > bc1 and bc2 vcc - 0.2v bc1 and bc2=v ih or s1=v ih or s2=v il 1.2 1.2 < = < = 10 c c s2 0.2v, other inputs = 0 ~ vcc < 2 > > =
mitsubishi electric m5m5v416btp,rt revision-p0 4 , ' 98.12.16 4194304-bit (262144-word by 16-bit) cmos static ram mitsubishi lsis preliminary notice: this is not a final specification. some parametric limits are subject to change ac electrical characteristics (vcc=2.7 ~ 3.6v, unless otherwise noted) input rise time and fall time reference level output loads 2.7v~3.6v v ih =2.4v,v il =0.4v v oh =v ol =1.5v transition is measured 500mv from steady state voltage.(for t en ,t dis ) 5ns fig.1,cl=30pf cl=5pf (for ten,tdis) (1) test conditions supply voltage input pulse 1ttl cl dq fig.1 output load including scope and jig capacitance t cr ns t a (s1) t a (oe) t dis (s1) t dis (oe) t en (s1) t en (oe) t v (a) t a (a) 10 70l,70h,70lw 70hw,70li,70hi 45 ns ns ns ns ns ns ns ns t a (bc1) t a (bc2) t dis (bc1) t dis (bc2) t en (bc1) t en (bc2) ns ns ns ns ns ns 85 85 85 85 30 30 30 30 10 10 5 10 100 10 50 100 100 100 100 35 35 35 35 10 10 5 10 t a (s2) ns 85 100 t en (s2) 10 ns 10 t dis (s2) ns 30 35 70 85 10 10 10 10 10 35 70 70 70 70 25 25 25 25 70 25 85l,85h,85lw 85hw,85li,85hi 10l,10h,10lw 10hw,10li,10hi 4 t su (a-wh) t cw t w (w) t su (a) t su (s1) t su (d) t h (d) t rec (w) t dis (w) t dis (oe) t en (w) t en (oe) ns 70 ns ns ns ns ns ns ns ns ns ns ns ns ns 55 0 65 25 25 5 5 t su (bc1) t su (bc2) 65 65 65 35 0 0 35 35 t su (s2) ns 65 70l,70h,70lw 70hw,70li,70hi 85l,85h,85lw 85hw,85li,85hi 10l,10h,10lw 10hw,10li,10hi 30 30 100 75 0 85 5 5 85 85 85 40 0 0 85 85 60 0 70 5 5 70 70 70 35 0 0 70 symbol parameter read cycle time limits address access time chip select 1 access time chip select 2 access time byte control 1 access time byte control 2 access time output enable access time output disable time after s2 low output disable time after s1 high output disable time after bc1 high max min max min max min units (2) read cycle output disable time after bc2 high output disable time after oe high output enable time after s1 low output enable time after s2 high output enable time after bc1 low output enable time after bc2 low output enable time after oe low data valid time after address (3) write cycle max min max min max min limits units write cycle time write pulse width address setup time byte control 1 setup time byte control 2 setup time chip select 1 setup time chip select 2 setup time data setup time data hold time write recovery time output disable time from w low output disable time from oe high output enable time from w high output enable time from oe low symbol parameter address setup time with respect to w
mitsubishi electric m5m5v416btp,rt revision-p0 4 , ' 98.12.16 4194304-bit (262144-word by 16-bit) cmos static ram mitsubishi lsis preliminary notice: this is not a final specification. some parametric limits are subject to change s2 (note3) (note3) t su (s2) t en (w) 5 t a (a) t a (bc1) t v (a) t dis (bc1) or t dis (bc1) t a (oe) t en (oe) t dis (oe) t cr t h (d) t su (d) dq 1~16 t su (bc1) or t su (bc2) t en (oe) t dis (oe) t w (w) t rec (w) t su (a) t dis (w) t cw t en (s1) w = "h" level a 0~17 dq 1~16 a 0~17 oe oe w (4)timing diagrams read cycle (note3) (note3) (note3) (note3) valid data write cycle ( w control mode ) data in stable (note3) (note3) t a (s1) t dis (s1) s1 (note3) (note3) bc1 , bc2 t a (bc2) or t en (bc2) t en (bc1) t su (a-wh) s1 (note3) (note3) t su (s1) bc1,bc2 t a (s2) t dis (s2) s2 (note3) (note3) t en (s2)
mitsubishi electric m5m5v416btp,rt revision-p0 4 , ' 98.12.16 4194304-bit (262144-word by 16-bit) cmos static ram mitsubishi lsis preliminary notice: this is not a final specification. some parametric limits are subject to change 6 note 3: hatching indicates the state is "don't care". note 4: a write occurs during s1 low, s2 high overlaps bc1 and/or bc2 low and w low. note 6: don't apply inverted phase signal externally when dq pin is in output mode. note 5: when the falling edge of w is simultaneously or prior to the falling edge of bc1 and/or bc2 or the falling edge of s1 t h (d) t su (d) dq 1~16 t su (bc1) or t su (bc2) t rec (w) t su (a) t cw a 0~17 w write cycle (bc control mode) data in stable (note3) (note3) (note4) (note5) (note3) (note3) s1 or rising edge of s2, the outputs are maintained in the high impedance state. bc1 , bc2 (note3) (note3) s2
mitsubishi electric m5m5v416btp,rt revision-p0 4 , ' 98.12.16 4194304-bit (262144-word by 16-bit) cmos static ram mitsubishi lsis preliminary notice: this is not a final specification. some parametric limits are subject to change t h (d) t su (d) dq 1~16 t su (s1) t rec (w) t su (a) t cw a 0~17 w s1 write cycle (s1 control mode) data in stable (note3) (note3) (note4) (note5) (note3) (note3) bc1 , bc2 (note3) (note3) s2 t h (d) t su (d) dq 1~16 t su (s2) t rec (w) t su (a) t cw a 0~17 w s1 write cycle (s2 control mode) data in stable (note3) (note3) (note4) (note5) (note3) (note3) bc1,bc2 (note3) (note3) s2 7
mitsubishi electric m5m5v416btp,rt revision-p0 4 , ' 98.12.16 4194304-bit (262144-word by 16-bit) cmos static ram mitsubishi lsis preliminary notice: this is not a final specification. some parametric limits are subject to change 8 t su (pd) t rec (pd) ns ms 2.2v t su (pd) 2.7v 2.7v 2.2v t rec (pd) bc1 , bc2 vcc - 0.2v vcc v v 2.0 vcc (pd) v i (s1) icc (pd) 2.0 bc1 -hw, -hi +70c +25 ~ +40c +70 ~ +85c -l, -lw, -li -h, -hw, -hi 0 ~ +25c -lw, -li -20 ~ +25c -40 ~ +25c -h -hw -hi 10 1 0.3 0.3 0.3 1 1 1 3 - - - - 20 20 40 - - - - - - - - a a a a a a a a power down characteristics (1) electrical characteristics symbol parameter test conditions limits min typ max units power down supply voltage chip select input s1 power down supply current vcc=3.0v (2) timing requirements symbol parameter test conditions limits min typ max units power down set up time power down recovery time (3) timing diagram bc control mode typical value is for ta=25 c v i (bc) byte control input bc1 & bc2 2) s1 vcc - 0.2v other inputs=0~3v 1) bc1 and bc2 vcc-0.2v s1 0.2v or s2 vcc-0.2v other inputs=0~3v > = < = > = v 2.0 > = bc2 2.2v t su (pd) 2.7v 2.7v 2.2v t rec (pd) vcc s1 s1 control mode s1 vcc - 0.2v > = 0 5 +40 ~ +70c +70 ~ +85c v v i (s2) chip select input s2 0.2 > = 3 ) s2 0.2v other inputs=0~3v 0 .2v t su (pd) 2.7v 2.7v 0 .2v t rec (pd) vcc s2 s2 control mode s2 0.2v
mitsubishi electric m5m5v416btp,rt revision-p0 4 , ' 98.12.16 4194304-bit (262144-word by 16-bit) cmos static ram mitsubishi lsis preliminary notice: this is not a final specification. some parametric limits are subject to change 9 revision history revision no. history date remark p01 the first edition '98 . 07 . 07 preliminary p02 pin#28: nc --> s2 '98 . 07 . 14 preliminary p03 font problem fixed '98 . 08 . 27 preliminary p04 70ns version added '98 . 12 . 16 preliminary
1.2 0.05 0.125 0.2 1.0 0.3 0.35 0.45 0.105 0.125 0.175 18.31 18.41 18.51 10.06 10.16 10.26 0.8 11.56 11.76 11.96 0.4 0.5 0.6 0.8 0.1 0 10 0.9 10.36 0.5 0.25 0.45 0.805 0.6 0.75 0.955 0.16 y 44 23 22 1 detail f f g detail g m e tsopii44-p-400-0.80 44p3w-h scale: 3/1 plastic 44pin 400mil tsop(ii) lead material weight(g) jedec code eiaj package code alloy 42 0.47 recommended mount pad a3 1 z y l 1 h e b 2 symbol min nom max a a 2 b c d e e l dimension in millimeters 1 a l 2 lp x z a 1 a 2 d a b a3 z z 1 e b 2 e x m
1.2 0.05 0.125 0.2 1.0 0.3 0.35 0.45 0.105 0.125 0.175 18.31 18.41 18.51 10.06 10.16 10.26 0.8 11.56 11.76 11.96 0.4 0.5 0.6 0.8 0.1 0 10 0.9 10.36 0.5 0.25 0.45 0.805 0.6 0.75 0.955 0.16 y 44 23 22 1 detail f f g detail g m e tsopii44-p-400-0.80 scale: 3/1 plastic 44pin 400mil tsop(ii) lead material weight(g) jedec code eiaj package code alloy 42 0.47 recommended mount pad a3 1 z y l 1 h e b 2 symbol min nom max a a 2 b c d e e l dimension in millimeters 1 a l 2 lp x z a 1 a 2 d a b a3 z z 1 e b 2 e x m 44p3w-j

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